A known a posteriori approach of the literature is used as a benchmark. Two a priori multiobjective extensions of Simulated Annealing are proposed, which differ in how the simultaneous use of a lexicographic order and weights is handled when evaluating the fitness. In addition, a preference model is introduced where trade-off is only allowed between some criteria. Because the solution approach must be embedded in a real-time application, decision makers must express their preferences before the optimization phase. A novel criterion on the satisfaction of production targets decided at a higher level is also proposed. To produce feasible and industrially meaningful schedules, this paper extends the recently proposed batch-oblivious approach by considering unavailability periods and minimum time lags and by simultaneously optimizing multiple criteria that are relevant in the industrial context.
![gunship iii steering on ground gunship iii steering on ground](http://www.joecustoms.com/customs/images/final/vehicle/2010/08/1281843284IMG_1479.jpg)
In this paper, we are concerned with the resolution of a multiobjective complex job-shop scheduling problem stemming from semiconductor manufacturing. The approach is validated by experiments based on a simulation model and industrial data. The local scheduling level aims to achieve the objectives set by the global scheduling models, while optimizing its own criteria and respecting its constraints. These global scheduling models correspond to different global scheduling strategies of the factory such as minimizing variability, controlling cycle times, etc. Different mathematical models called global scheduling models (linear programs) proposed in the thesis determine these quantities. These production targets are expressed as the quantities of components to be achieved for each operation and for each period over a scheduling horizon. This approach aims at steering scheduling decisions at the work center level using production targets.
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Thus, this thesis proposes a global scheduling approach based on a structure in two levels of the operational level (global level and local level). It is therefore very difficult to manage in detail all of the scheduling decisions in all the work centers of a factory. These characteristics, along with reentrant flows and long cycle times (6 to 8 weeks) greatly complicate scheduling decisions. Each work center specializes in handling one type of operation, and these are usually very different from one work center to another. In semiconductor manufacturing, microelectronic components require several hundred operations on several hundred machines grouped into different work centers. Analyses and simulations exploiting fab data show that TaTIV sets targets closer to what are actually achieved at individual steps than those set without considering TIV, reduces inter-step variations of machine allocation, and improves fab throughput and cycle times.
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#Gunship iii steering on ground trial#
TaTIV integrates three innovations: i) a Bernoulli trial model for approximating TIV of MALD at a process step under a given target, ii) a hybrid and recursive tandem queue approximation of multiple-step target-induced wafer flows and flow times given initial WIPs and machine group capacities of the day, and iii) a fixed-point iteration between target setting and target-induced wafer flow estimation. A novel design of target-setting algorithm considering TIV called TaTIV is proposed to take TIV into account for setting daily targets systematically. Existing approaches do not explicitly address such target-induced variations (TIV), and the resultant target setting may incur throughput loss and prolonged cycle times.
![gunship iii steering on ground gunship iii steering on ground](http://www.joecustoms.com/customs/images/final/vehicle/2010/08/1281843284IMG_1475.jpg)
Operations of individual machine groups will track their respective target guidance through detailed machine allocation and lot dispatching (MALD), inducing variations of wafer flow. Daily production target setting based on machine capacities and available wafer-in-process (WIP) is an important practice in a semiconductor fab characterized by re-entrant process steps sharing individual machine group capacities.